1. Field of Invention
This invention relates to a semiconductor package and manufacturing method thereof and, in particular, to a semiconductor package of wafer level chip size packages (CSP) and manufacturing method thereof.
2. Related Art
The high integration of ICs combined with the urgent consumption requirements of the market has resulted in a trend toward more compact and lightweight semiconductor packages. Currently there are a variety of semiconductor package technologies, which are disclosed. Widely used packages include Pin Grid Array (PGA) packages, Ball Grid Array (BGA) packages, wafer level CSPs, and the likes.
In the mentioned packages, since the surface of a BGA type semiconductor package 1 (as shown in FIG. 1) is efficiently employed, the BGA type semiconductor package 1 has more solder balls 13 provided on the surface of the substrate 11. Therefore, the solder balls 13 are able to make an electrical connection to the pads (not shown) on the semiconductor die 12 via trace lines and fingers provided by the BGA type semiconductor package 1. In the BGA type semiconductor package 1, more fingers are used, so that the semiconductor die 12 and outwards could communicate to each other via the solder balls 13.
Compared to the BGA type semiconductor package 1, a wafer level CSP type semiconductor package employs a smaller substrate with fewer leads formed around the semiconductor die. Put simply, the amount of leads available in wafer level CSP type semiconductor packages is limited.
For example, wafer level CSP type semiconductor packages usually include Quad Flat No-Lead (QFN) type semiconductor packages and Bump Chip Carrier (BCC) type semiconductor packages. In such cases, the lead frame has a bottom surface for electrically connecting with a mother board, making extra conductive components, such as trace lines and fingers, unnecessary. Thus, the objective of minimizing semiconductor packages can be carried out. In general, wafer level CSP type semiconductor packages are compact and light, so they are often used in electronic devices such as personal computers, digital cameras, and mobile phones.
Please refer to FIGS. 2A and 2B, for a representation of a conventional QFN type semiconductor package 2, which includes a die pad 21, a semiconductor die 22, a lead frame 23, a plurality of wires 24, and a molding compound 25. In this case, the semiconductor die 22 is attached to the die pad 21. The semiconductor die 22 and lead frame 23 respectively have a plurality of pads 221 and leads 231, and each of the wires 24 is used to bond each pad 221 to each corresponding lead 231. The molding compound 25 covers the die pad 21, semiconductor die 22, lead frame 23, and wires 24. It should be noted that the molding compound 25 does not cover the bottom surfaces of the die pad 21 and lead frame 23. Therefore, the QFN type semiconductor package 2 is able to make an electrical connection with the mother board (not shown) via the bottom surface of the lead frame 23.
As mentioned above, the molding compound 25 is made of thermosetting material, which can be cured under high temperature. Each of the leads 231 has a surface coated with a metallic material such as tin or Ni—Pd alloys for electrically connecting with one of the wires 24. Therefore, the welding qualities between the wires 24 and leads 231 are improved, and the chemical reactions between the wires 24 and leads 231 can be prevented.
The conventional die pad 21, however, is a single layer structure and is only used for carrying the semiconductor die 22. Thus, there is no lead provided on the bottom surface of die pad 21. Put simply, the QFN type semiconductor package 2 cannot have as many solder balls as the BGA type semiconductor package 1 (as shown in FIG. 1). Furthermore, people skilled in the art should known that any other wafer level CSP type semiconductor package, such as a BCC type semiconductor package, will also not have as many solder balls as the BGA type semiconductor package 1.
Hence, to increase leads during performing wafer level CSP packaging, it is necessary to enlarge the size of a wafer level CSP type semiconductor package. However, once the size is enlarged, the semiconductor package is unsuitable for the compact electronic devices, for which the wafer level CSP is commonly used. Alternatively, people skilled in the art might reduce the pitches between the leads to solve the above-mentioned problem, but this will decrease the yield of semiconductor packages while performing SMT processes.
It should also be noted that although the BGA type semiconductor package provides more leads, the cost of a BGA type semiconductor package is relatively higher than that of a wafer level CSP type semiconductor package.
Therefore, it is an important subjective of the invention to increase the number of leads without enlarging the size of a semiconductor package, and to improve the yield while manufacturing semiconductor packages.